| 1. | Standard test access port and boundary scan architecture
标准测试存取口及边界扫描体系结构 |
| 2. | Application of boundary scan technique to the design for board - level test
边界扫描技术在板级可测性设计中的应用 |
| 3. | The article also addresses the mechanism of vector creation for boundary scan
本文进一步分析了边界扫描测试矢量生成机制。 |
| 4. | Boundary scan aims at the test of application system , e . g . pcb test
边界扫描测试是针对芯片的应用系统进行测试的，如pcb板测试。 |
| 5. | As a kind of new developing bit technology , boundary scan technology is widely used in industry
边界扫描技术作为一种新兴的bit技术,在工业界内得到了广泛的应用。 |
| 6. | A plan of design for test based of boundary scan testing is introduced for this signal processing system
接着，提出了该信号处理系统基于边界扫描的可测性设计方案。 |
| 7. | International standard ieee 1149 . 1 describes the basic circuit structure and performance of boundary scan
国际标准ieee1149 . 1规定了边界扫描的基本电路结构和功能。 |
| 8. | Jx5 microprocessor ’ s testing structure comprises built - in self - test ( bist ) , boundary scan and internal scan
Jx5微处理器的测试结构由bist 、边界扫描和内部扫描三部分组成。 |
| 9. | In this paper , we combine the standard modules realize the boundary scan of estarl and also expand it to the test of internal circuit . this structure can save the i / o port of the chip and simplify the testing program
本文结合标准模块设计实现了estar1的边界扫描结构，并进行了扩展，应用到芯片内部测试，节约了测试i / o口消耗，简化了测试过程。 |
| 10. | In this paper we investigate and carry out boundary scan ^ internal scan and built - in self - test three dft technologies in the embedded microprocessor estarl and get satisfying result , the fault coverage is more than 96 %
本文针对嵌入式微处理器estar1的结构特点，研究并实现了边界扫描、内部全扫描和内建自测试三种可测性设计技术，取得了良好的效果，故障覆盖率达到96以上。 |
